library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity template is port( reset_n : in std_logic; clk : in std_logic; ); end template; architecture twoproc of template is type state_type is (S_READY, S_BUSY); constant SOME_MAX : integer := 15; type register_rec is record state : state_type; --foo : unsigned(1 downto 0); --bar : integer range 0 to SOME_MAX; --baz : std_logic_vector(31 downto 0); end record; constant reset_values: register_rec := ( state => S_READY, baz => (others => '0') ); -- Current and Next Register State signal r, rin : register_rec; begin logic_proc: process(all) variable v : register_rec; begin ----------------------------------------------------------------------- -- Default Statement ----------------------------------------------------------------------- v := r; ----------------------------------------------------------------------- -- Logic / FSM ----------------------------------------------------------------------- case r.state is when S_READY => v.state := S_BUSY; when S_BUSY => v.state := S_READY; end case; ----------------------------------------------------------------------- -- New Register Input / Variable to Output ----------------------------------------------------------------------- rin <= v; ----------------------------------------------------------------------- -- Drive Outputs ----------------------------------------------------------------------- end process; reg_proc: process(clk, reset_n) begin if reset_n = '0' then r <= reset_values; elsif rising_edge(clk) then r <= rin; end if; end process; end twoproc;